Structure of a non-volatile memory device and operation method

ABSTRACT

A nonvolatile memory device includes composite gate structures formed on a substrate in series along a bit line direction. The composite gate structure has a first storage gate structure, a second storage gate structure, and a selection gate between the two storage gate structures. Each of the composite gate structures is respectively coupled to two world line connection terminals at the two storage gate structures and a selection terminal at the selection gate. Each of the storage gate structures corresponds to a memory bit cell. Multiple doped regions are in the substrate between the composite gate structures. A first selection doped region are formed in the substrate and coupled between a BL connection terminal and a first edge one of the composite gate structure. A second selection doped region is formed in the substrate and coupled between a second edge one of the composite gate structures and a voltage terminal.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of a prior application Ser.No. 11/154,378, filed Jun. 15, 2005. All disclosures are incorporatedherewith by reference.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to memory device. More particularly, thepresent invention relates to a technology for fabricating thenon-volatile memory device.

2. Description of Related Art

The non-volatile memory, such as flash memory device, allows multipletimes erase and program operation inside system. As a result, flashmemory is suitable to many of advance hand-held digital equipments,including solid state disks, cellar phones, digital cameras, digitalmovie cameras, digital voice recorders, and PDA, that are demanding alow-cost, high-density, low-power-consumption, highly reliable filememory.

Conventional technology is a NAND type flash memory with memorytransistors connected in series by way of N+ impurity diffusion layer.FIG. 1A is a cross-sectional view, illustrating the semiconductorstructure of the conventional NAND flash memory. In FIG. 1A, thesubstrate 100 usually has logic device region and the memory deviceregion with the doped well with desired conductive type. In thefollowing descriptions, only the memory region is described. Thesubstrate for example has the N-type doped well DNW 100 and then ap-type doped well TPW 102 is formed within the DNW 100. The string ofNAND memory cells are then formed on the P-type well 102. Each of thememory cells 0, 1, 2, . . . , n−1 has the gate structure 112, includingthe floating gate and the control gate, as known by the ordinary skilledartisans. The source/drain (S/D) doped region 104 is formed in thesubstrate 100 at each side of the gate structure. Two selectiontransistors 114 and 116 are coupled at the beginning and the end of thememory string. The selection transistor includes the gate electrode andthe S/D regions at each side of the gate electrode. The S/D region 106of the first selection transistor 114 is coupled to the bit line (BL)voltage while the S/D region 110 of the last selection transistor 116 iscoupled to a voltage VS.

The operation of the NAND type memory is described. FIGS. 1B-1D are theoperations of program, erase, and read based on the structure in FIG.1A. In FIG. 1B, for example, the cell 0 is to be programmed. The bitline voltage is set to ground GND and applied to the S/D region 106. TheS/D region 110 of the selection transistor 116 is also set to a groundvoltage GND. The gate electrode of the selection transistor 114 set to atrigger voltage VCC to turn on the transistor, so as to allow the bitline voltage to pass to the doped region 105, which also serves as theS/D region 104 of the cell 0. The other cells 1, 2, . . . , n−1 are alsoturned on by applying a voltage ½ VPP, such as 10 V on the gateelectrode, so as to pass the ground voltage at the S/D region 110 to thecell 1. The gate electrode of the cell 0 is applied with the voltage ofVPP, such as 20 V. As a result, electrons are injected into the floatinggate of the gate structure 112 to program the cell 0.

In FIG. 1C, when the erase operation is performed, all of the gatestructures 112 are set to ground voltage GND. The selection transistorsare also turned on but the S/D regions are at floating state. However,the p-type well 102 is applied a high voltage VPP. As a result, theelectrons stored in the floating gate of the gate structure are drivento the substrate, and then the stored information in any one of thememory cells is erased.

In FIG. 1D, when the read operation is performed, in which the memorycell 0 is for example to be read, the gate structures 112 of the memorycells 1, 2, . . . , n−1 are applied to a pass voltage Vpass, such as 7V,so that the ground voltage at the S/D region 110 is passed to theadjacent S/D region 104 of the memory cell 0. The control gate of thegate structure 112 of the memory cell 0 is applied the ground voltageGND. However, the floating gate still carries positive voltage to turnon the memory cell 0 due to electrons being pulled out of the floatinggate, if this memory cell has currently been programmed to “1”. Thep-type well 102 is applied a ground voltage of GND. The BL line at theS/D region 106 then senses the conductive state of this memory string.

For the conventional NAND memory cell, it at least has severaldisadvantages. For example, device operation of this memory cell adoptschannel FN programming and erase. The disadvantages includes, forexample, the program speed is lower than that with channel hot electron.Also and, it needs an extra selection transistor on source side. Inaddition, the cell gate between two N+ impurity layers is difficult toshrink due to short channel effect. In brief, the disadvantages includesthe low programming speed due to FN tunneling, the junction to junctionleak for the programmed cell, and the extra selection transistor onsource side of the for programming.

SUMMARY OF THE INVENTION

The invention provides a novel non-volatile memory device, such as theflash memory device, the foregoing conventional disadvantages can atleast be significantly solved. As a result, the operation speed can beeffectively improved and the current leakage can be reduced. Also and,only one doped region is needed for one memory cell, so that the devicesize can be effectively reduced.

The present invention provides a nonvolatile memory device, whichincludes composite gate structures formed on a substrate in series alonga bit line (BL) direction. Each of the composite gate structurescomprises a first storage gate structure, a second storage gatestructure, a selection gate between the two storage gate structures, andan insulating layer for isolating the various gates. Each of the storagegate structures corresponds to a memory bit cell. A plurality of dopedregions is in the substrate between the composite gate structures. Afirst selection doped region is formed in the substrate, coupled betweena first BL connection terminal and a first edge one of the compositegate structures. A second selection doped region is formed in thesubstrate, coupled between a second BL connection terminal and a secondedge one of the composite gate structures. Each of the storage gatestructures of the composite gate structures includes a charge storagelayer over the substrate and a control gate over the charge storagelayer.

According to the further aspect of the invention, the two control gatesof the two storage gate structures together are an integrated gate layeralso over the selection gate, so that the two control gates areelectrically connected.

According to the further aspect of the invention, the two control gatesof the two storage gate structures are structurally separated at bothsides of the selection gate.

The present invention further provides a semiconductor structure ofdual-bit memory cell, comprising a first storage gate structure over asubstrate; a second storage gate structure over the substrate; aselection gate over the substrate between the first and the secondstorage gate structures; a first doped region, in the substrate at anouter side of the first storage gate structure; and a second dopedregion, in the substrate at an outer side of the second storage gatestructure. The first storage gate structure and the second storage gatestructure are a stack gate structure including a charge storage layerand a control gate over the charge storage layer.

The present invention further provides an operation method of theforegoing nonvolatile memory device, comprising applying a set ofreading voltages on the composite gate structures, the first selectiondoped region and the second selection doped region, for a read operationon a selected reading cell. Then, a set of programming voltages isapplied on the composite gate structures, the first selection dopedregion and the second selection doped region, for a program operation ona selected programming cell. A set of erasing voltages is applied on thecomposite gate structures, the first selection doped region and thesecond selection doped region, for an erase operation on a selectederasing cell.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1A is a cross-sectional view, schematically illustrating thesemiconductor structure of a conventional NAND type nonvolatile memorydevice.

FIGS. 1B-1D are the drawings, schematically illustrating the operationsof read, program, and erase with respect to the structure in FIG. 1A.

FIGS. 2A-2B are circuit drawings, schematically illustrating an arraystructure of the nonvolatile memory device, according to an embodimentof the invention.

FIGS. 3A-3B are circuit drawings, schematically illustrating an arraystructure of the nonvolatile memory device, according to anotherembodiment of the invention.

FIGS. 4A-4B and 5A-5B are cross-sectional views, schematicallyillustrating the various semiconductor structures of a NAND typenonvolatile memory device, according the embodiment of the invention.

FIGS. 6 and 7 are top-view drawings, schematically illustrating a layoutof the nonvolatile memory devices as shown in FIGS. 4-5.

FIG. 8A is the drawing, schematically illustrating the programoperations, according to the embodiment of the invention.

FIG. 8B is the drawing, schematically illustrating the read operations,according to the embodiment of the invention.

FIG. 8C is the drawing, schematically illustrating the erase operations,according to the embodiment of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention is directed a novel volatile memory device. In order toperform good reliability, the structure of the memory array is proposed,as shown in FIGS. 2A-2B and FIGS. 3A-3B. About the general properties ofthe invention, the novel memory device is an NAND Type arrayarchitecture with memory transistors connected in series by way ofn+impurity layer and select gate in turn along the bit line. Theadvantage of this cell compared to conventional NAND memory device isthat the source side hot electron can be adopted in this novelnonvolatile memory device. The source side hot electron program canprovide very high program speed and low program current. The novelmemory device can has one selection transistor on BL side or twoselection transistors on both side of memory array. It is easy to shrinkthe cell gate due to only one impurity layer for one cell, while thereare two impurity layers on both sides of cell gate for conventional NANDflash.

FIGS. 2A-2B are circuit drawings, schematically illustrating an arraystructure of the nonvolatile memory device, according to an embodimentof the invention. In FIG. 2A, the memory cell employ a stack gate as thestorage gate structure for storing the information, in which the stackgate usually includes, for example, the charge storage layer for storinginformation and the control gate on the charge storage layer forcontrolling the cell to drive electron in or out from the charge storagelayer. The charge storage layer can include a proper material forstoring charges. The material includes, for example, nitride layer to beSONOS (silicon-oxide-nitride-oxide-silicon) cell. Further, the nitridelayer, such as SiN layer, of the memory cell can be replaced to anydielectric layer that can capture or store electron and hole duringprogram and erase operation, like Si rich SiN, tantalum oxide (Ta₂O₅),Aluminum oxide (Al₂O₃), or even like nano-crystal Silicon. The chargestorage layer preferable is a stacked structure, in which a chargetrapping layer is between a bottom oxide layer and a top oxide layer.The control gates are coupled to the corresponding word lines. Forexample, the control gate 0 (CG0) is coupled to the word line 1 (WL1)and the control gate 1 (CG1) is coupled to the word line 2 (WL2). In theinvention, the adjacent two memory bit cells are implemented with aselection gate, such as SG1 with respect to CG0 and CG1, so that adual-bit memory cell can be formed. The desired source/drain (S/D)regions can be applied to the bit line terminals BL0_D, BL1-D, . . .BLn−1_D in a memory block, and the source terminal at the other end ofthe bit line terminals. The S/D regions are passed to the selected cell,so as to form a result equivalent to a single MOS memory cell with acomposite gate structure. The select gate (SG) is used with the controlgate to access one bit of the memory cell, according to the currentdirection in the bit line. The equivalent semiconductor structure andoperations will be described later. In FIG. 2A, it is just an example ofthe invention. Alternatively, for example, one of the selectiontransistor, such as SGD2 in FIG. 2A, can be omitted. Instead, a powerterminal can be directly applied to the S/D region of the edge one ofthe composite gate.

FIGS. 3A-3B circuit drawings, schematically illustrating an arraystructure of the nonvolatile memory device, according to anotherembodiment of the invention. In FIG. 3A, it is similar to the circuitstructure in FIG. 2A but the two control gates in one composite gatestructure are connected together. Therefore, for one dual-bit cell, onlyone control gate (CG) is needed in control. The equivalent semiconductorstructure and operations will be described later. Likewise, FIG. 3Bshown another example by omitting one selection transistor.

FIGS. 4A-4B and 5A-5B are cross-sectional views, schematicallyillustrating the various semiconductor structures of a NAND typenonvolatile memory device, according the embodiment of the invention. InFIG. 4A, the semiconductor structure alone one bit line is equivalent toFIG. 2A. On a substrate 300, the composite gate structure includes twostorage gate structures 310 and a select gate structure having a selectgate 302 and a gate dielectric layer 304. The two storage gatestructures 310 are at both sides of the select gate structure and areisolated by the dielectric layer 312. The storage gate structure 310includes a control gate 306 and a charge storage layer 308. The chargestorage layer 308, as mentioned above, can include for example a bottomdielectric layer, a charge trapping layer, and a top dielectric layer.The charge storage layer 308 can have various options, which aredescribed one by one here, but can be known by the one with ordinaryskill in the art.

A doped region 313, serving as S/D region, is formed in the substratebetween the composite gate structures. For the first-edge one of thecomposite gate structures, such as the one with control gate CG0, isconnected with a selection transistor, having the select gate 314, agate dielectric layer 315, and the S/D regions 316 and 318. The S/Dregion 316 may be commonly used with the first-edge one of the compositegate structures. Likewise, the second-edge one of the composite gatestructures, such as the one with control gate CG 2 n−1, is connectedwith another selection transistor, having the select gate 322, a gatedielectric layer 323, and the S/D regions 324 and 326. The S/D region326 may be commonly used with the second-edge one of the composite gatestructures. For the transistor string, the two selection transistors aresymmetric, and can be alternatively serve as the drain region, and thesource region, according to the applied voltage for producing a currentdirection. In FIG. 4A, the doped region 318 of one selection transistorserves as a bit line terminal BL_D, which can be applied with a drainvoltage. The other doped region 324 of the other selection transistorserves as a bit line terminal BL_S, which can be applied with a drainvoltage. According to the actual operation to access one bit of thedual-bit memory cell, the current direction, caused by the sourcevoltage and the drain voltage, determines the desired bit. As previousdescription, FIG. 4B shows the schematic semiconductor structure for thealternative situation in omitting one selection transistor. The S/Dregion 326 is directly coupled to a power terminal VS.

In FIG. 5A, the composite gate structure is similar to the compositegate structure in FIG. 4A but the two control gates are connectedtogether. The composite gate structure includes the select gatestructure and two storage gate structures. Taking the first-edge one ofthe composite gate structure as the example, the select gate structureinclude a select gate 402 and a gate dielectric layer 404 on thesubstrate 400. Each of the two storage gate structures includes thecontrail gate 410 and the charge storage layer 408. The charge storagelayer 408 is similar to the charge storage layer 310 in FIG. 4A.However, preferably, the two control gates are connected together, suchas a single control layer. The insulating layer between the variousgates is for isolation. Likewise, the edge one of the composite gatestructures is connected to a selection transistor with the select gate314, gate dielectric layer 413, S/D regions 414, 416, while the otheredge one of the composite gate structures is connected to a selectiontransistor with the select gate 420, gate dielectric layer 421, S/Dregions 422, 424. As previous description, FIG. 5B shows the schematicsemiconductor structure for the alternative situation in omitting oneselection transistor. The S/D region 424 is directly coupled to a powerterminal VS.

FIGS. 6 and 7 are top-view drawings, schematically illustrating a layoutof the nonvolatile memory devices as shown in FIG. 4A and FIG. 5A. Here,only a portion of the full memory array is shown. In FIG. 4A and FIG. 6,the cross-sectional view of the NAND bit line 500 is shown in FIG. 4A.The select gate 314 in FIG. 4A is equivalent to the select gate line502. The composite gate structure includes two storage gate structurelines 504 and a select gate line 506. The charge storage layer at theregions 510 serve as the memory bit cells. In FIG. 5A and FIG. 7, thecross-sectional view of the NAND bit line 600 is shown in FIG. 5A. Theselect gate 314 in FIG. 5A is equivalent to the select gate line 602.The composite gate structure includes one storage gate structure line604 with two storage gate structures and a select gate line 606. Thecharge storage layer at the regions 608 serve as the memory bit cells.The storage gate structure line 604 is indicated by CG1 while the selectgate line 606 is indicated by SG1, in FIG. 5A.

Now, operations of the memory device are, for example, described asfollows. FIG. 8A is the drawing, schematically illustrating the programoperations, according to the embodiment of the invention. Taking thestructure in FIG. 2 and FIG. 4A as the example for descriptions, if theright bit cell of the composite gate structure with select gate SG1 isintended to be programmed, shown in upper drawing, the drain voltage VDis applied to the bit line terminal BL_D while the source voltage, suchas ground voltage, is applied to the bit line terminal BL-S (or VS). Thecontrol gate line CG2 is applied with a program voltage VPGM, the selectgate line is applied with a turning-on voltage VON, the other controlgate lines are applied with a voltage VPP2. The select gate lines areapplied with a voltage VPP1. The voltages VPP1 and VPP2 are used tocause underneath region of the substrate to be changed to performing thefunction of channel, so that the source voltage and the drain voltagecan be passed to the S/D regions beside the control gate CG2 having theprogram voltage VPGM. As a result, for example, the electrons aretrapped into charge trapping layer under the corresponding control gateCG2. Alternatively, if the left bit cell is to be programmed, as shownin lower drawing, the mechanism is similar but the current directioncaused by the source voltage (GND) and the drain voltage (VD) arereversed. The control gate line CG3 is applied with the program voltageVPGM.

FIG. 8B is the drawing, schematically illustrating the read operations,according to the embodiment of the invention. In FIG. 8B, the readoperation is shown. If the right bit cell is to be read, shown in upperdrawing, the bit line terminal BL_S (or VS) is applied with the voltageVD while the bit line terminal BL_D is applied with the ground voltageGND. The control gate line CG2 is applied with a reads voltage VR, withthe other gates are applied the voltage BPP1 or VPP2 for passing thesource voltage and the drain voltage to the S/D regions beside thecontrol gate line CG2. The read direction with respect to electrons isindicated by arrow. Alternatively, if the left bit cell under thecontrol gate line CG3 is to be read, shown in lower drawing, thevoltages are arranged in reverse direction. The voltage VD is applied tothe bit line terminal BL_D while the ground voltage is applied to thebit line terminal BL_S (or VS).

FIG. 8C is the drawing, schematically illustrating the erase operations,according to the embodiment of the invention. In FIG. 8C, if the memoryis to be erased, it usually has two mechanisms based on the mechanism ofband to band hot hole erase, or FN erase. For the band to band hot holeerase, it is shown in upper drawing, both the bit line terminals BL_Dand BL_S (VS) are applied with the erase voltage VER, while theselection gate SG1 is applied with a ground voltage GND and the controlgate line is applied with a voltage, such as the voltage VR. As aresult, the hot holes h+ are driven into the charge trapping layer toneutralize the electrons. Alternatively, based on the FN erase shown inlower drawing, both the bit line terminals BL_D and BL_S (VS) areapplied with the ground voltage GND. The control gate lines CG2 and CG3are applied with a negative voltage, such as −VER, so as to drive thetrapped electrons into the substrate. The substrate is applied with arelative positive voltage to allow the electrons to flow into thesubstrate and then to the ground terminals.

It should be noted that, the operation voltages for programming, readingand erasing can be changed, and are not limited to the foregoingexamples. The operation voltages can be properly set, based on thestructure of the invention.

Further, if the memory cell structure is taking the structure in FIG.5A, then it is shown in FIG. 3. The access mechanism is the same but thecontrol gate line CG2 and CG3 in FIG. 2 can be treated as a same voltageof VPGM or VR in FIG. 8A and FIG. 8B. Both the control gate are appliedwith the same voltage, it can simplify the operation. However, it may bea little higher error rate in accessing cell.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing descriptions, it is intended that the presentinvention covers modifications and variations of this invention if theyfall within the scope of the following claims and their equivalents.

1. A structure of a nonvolatile memory device, comprising: a pluralityof composite gate structures formed on a substrate as a string along abit line (BL) direction, wherein each of the composite gate structurescomprises a first storage gate structure, a second storage gatestructure, a selection gate structure between the two storage gatestructures, wherein each of the storage gate structures corresponds to amemory bit cell; a plurality of doped regions in the substrate betweenthe composite gate structures; a first selection doped region, formed inthe substrate, coupled between a first BL connection terminal and afirst edge one of the composite gate structures; and a second selectiondoped region, formed in the substrate, coupled between a second BLconnection terminal and a second edge one of the composite gatestructures, wherein each of the storage gate structures of the compositegate structures includes a charge storage layer over the substrate and acontrol gate over the charge storage layer.
 2. The structure of claim 1,wherein the two control gates of the two storage gate structures arestructurally separated at both sides of the selection gate.
 3. Thestructure of claim 1, wherein the two control gates of the two storagegate structures together are an integrated gate layer also over theselection gate, so that the two control gates are electricallyconnected.
 4. The structure of claim 1, wherein each of the chargestorage layers comprises nitride, Si rich SiN, tantalum oxide (Ta₂O₅),aluminum oxide (Al₂O₃), or nano-crystal Silicon.
 5. The structure ofclaim 1, wherein the charge storage layer is a stacked layer, comprisinga bottom oxide layer, a top oxide layer and a middle charge trappinglayer between the bottom oxide layer and the top oxide layer.
 6. Thestructure of claim 1, further comprising: a first source/drain (S/D)selection transistor, coupled to a first edge one of the composite gatestructures; and a second S/D selection transistor, coupled to a secondedge one of the composite gate structures, wherein the first S/Dselection transistor and the second S/D selection transistorrespectively pass a source voltage and a drain voltage to a selected oneof the composite gate structures, so as to access a corresponding one ofthe memory bit cells.
 7. The structure of claim 1, further comprising: asource/drain (S/D) selection transistor, coupled to a first edge one ofthe composite gate structures; and a doped S/D region, coupled to asecond edge one of the composite gate structures, without coupling toadditional selection transistor. wherein the S/D selection transistorand the doped S/D region respectively pass a source voltage and a drainvoltage to a selected one of the composite gate structures, so as toaccess a corresponding one of the memory bit cells.
 8. The structure ofclaim 6, wherein is a current direction caused by the source voltage andthe drain voltage determines the corresponding one of the memory bitcells being accessed.
 9. The structure of claim 7, wherein is a currentdirection caused by the source voltage and the drain voltage determinesthe corresponding one of the memory bit cells being accessed.
 10. Asemiconductor structure of dual-bit memory cell, comprising: a firststorage gate structure over a substrate; a second storage gate structureover the substrate; a selection gate over the substrate between thefirst and the second storage gate structures; a first doped region, inthe substrate at an outer side of the first storage gate structure; anda second doped region, in the substrate at an outer side of the secondstorage gate structure, wherein the first storage gate structure and thesecond storage gate structure are a stack gate structure including acharge storage layer and a control gate over the charge storage layer.11. The semiconductor structure of claim 10, wherein the control gatesof the first storage gate structure and the second storage gatestructure are structurally separated.
 12. The semiconductor structure ofclaim 10, wherein the control gates of the first storage gate structureand the second storage gate structure are structurally connected as asingle structural layer.
 13. The semiconductor structure of claim 10,wherein the charge storage layer comprises nitride, Si rich SiN,tantalum oxide (Ta₂O₅), aluminum oxide (Al₂O₃), or nano-crystal Silicon.14. The semiconductor structure of claim 10, wherein the charge storagelayer is a stacked layer, comprising a bottom oxide layer, a top oxidelayer and a middle charge trapping layer between the bottom oxide layerand the top oxide layer.
 15. An operation method of a nonvolatile memorydevice as recited in claim 1, comprising: applying a set of readingvoltages on the composite gate structures, the first selection dopedregion and the second selection doped region, for a read operation on aselected reading cell; applying a set of programming voltages on thecomposite gate structures, the first selection doped region and thesecond selection doped region, for a program operation on a selectedprogramming cell; and applying a set of erasing voltages on thecomposite gate structures, the first selection doped region and thesecond selection doped region, for an erase operation on a selectederasing cell.
 16. The operation method of claim 15, wherein in the setof programming voltages in the program operation, the selection gate ofthe selected programming cell is applied with a voltage greater than athreshold voltage, so as to constrain a programming current to flowthrough the selected programming cell in a corresponding one of thecomposite gate structures.
 17. The operation method of claim 15, whereindesired voltages for S/D voltages are applied at the first selectiondoped region and the second selection doped region, and are passed tothe selected programming cell, the selected reading cell, or theselected erasing cell.
 18. The operation method of claim 15, wherein inthe erase operation, all information stored in an array block of thememory bit cells is erased at the same time.
 19. The operation method ofclaim 15, wherein the two control gates of the two storage gatestructures are structurally separated at both sides of the selectiongate, and are applied with different voltage levels.
 20. The operationmethod of claim 15, wherein the two control gates of the two storagegate structures together are an integrated gate layer also over theselection gate, so that the two control gates are electricallyconnected, and are therefore applied with a same voltage level.